The present invention relates generally to memory integrated circuits. More particularly, the present invention relates to method and apparatus for equalizing the width of an address transition detection signal in a memory integrated circuit.
In many memory integrated circuits, it is known to use an address transition detection (ATD) circuit to generate an ATD signal. Such memories receive a multiple bit address signal as an input specifying a location for access of data stored in the memory. The address signal is typically received at a plurality of address buffers. Each address buffer provides signal translation and buffering and generation of true and complement signals for subsequent address decoding. In response to any transition of any bit of the input address signal, the ATD circuit generates the ATD signal. In addition to the address inputs, other signal inputs will cause generation of the ATD signal by the ATD circuit. These signal inputs include chip enable signals and write enable signals which control the operation of the memory integrated circuit.
It is conventional to generate an ATD signal that is a pulse of predetermined polarity and has predetermined time duration. For example, the ATD signal may normally have a logic 0 level until an address transition occurs. In response to the address transition, a pulse having a logic 1 level is generated by the ATD circuit. The pulse has a duration, such as 1 microsecond, which is controlled by timing elements of the ATD circuit. If subsequent address transitions occur during the pulse duration, the pulse timing is reset to ensure the full duration of the pulse.
The ATD signal provides a convenient timing reference. Many other internal signals are timed in response to the timing of the ATD signal. These other signals include decoding of the input address to select a unique storage location within the memory for storage or retrieval of data. These other signals include a word line supply voltage used for read access of a storage location. A change of an address signal produces a timing reference for subsequent operations in the memory integrated circuit.
However, different operations and the physical layout of the memory integrated circuit can alter the width or duration of the ATD pulse. Many memory integrated circuits are arranged with some address buffers at one end of the chip and other address buffers at the other end of the chip. Internal operations, such as automatic power-down functions, can change the operation of the ATD circuit and therefore the width of the ATD pulse.
It is desirable, however, for optimum and consistent operation of the memory integrated circuit, to have a uniform pulse width for the ATD signal. Accordingly, there is a need for an improved method and apparatus providing equalized pulse width of an address transition signal in a memory integrated circuit.
By way of introduction only, the present invention provides an improved method and apparatus for providing equalized pulse width in an address transition detector (ATD) signal in a memory. By careful circuit and layout design, capacitive loading on intermediate ATD signals is reduced to sharpen the voltage transitions on these intermediate ATD signals. A feedback delay circuit is added to the ATD signal generating circuit to define the duration of the ATD pulse. This equalizes the ATD pulse duration, regardless of the source of the address transition signal.
The foregoing discussion of the preferred embodiments has been provided only by way of introduction. Nothing in this section should be taken as a limitation on the following claims, which define the scope of the invention.